IN VHDL PROGRAMMING

Problem 1. Professor FSM Prof has 3 activities, Grading Exams, Doing Housework, and Zoning to Netflix. Prof has 2 inputs that determine the activity, Coffee and Exams. Prof has 2 outputs from the activities, Grades and Housework When Prof has Exams, Prof will be Grading Exams for at least one cycle. While Prof has Coffee, Prof will continue Grading Exams until there are no more Exams input. If Prof runs out of Coffee, Prof will tire of grading exams after one cycle and transition to watching Netflix. When Grading Exams, Prof will output Grades. When Prof has Coffee and no Exams, Prof will be Doing Housework. While Doing Housework, Prof will output Housework. When Prof has no Coffee and no exams, Prof will binge-watch Netflix and output nothing (don't judge!). Upon waking up, Prof will start in the Zoning to Netflix state. (I said don't judge!) Prof has no other inputs, outputs, or activities. Due to their high level of academic training, Prof. will never enter into an illegal state. The Prof, being a highly tuned and precisely engineered machine, will transition states every second. Implement your Prof FSM on your Basys3 and demonstrate it in class. Include a state diagram in your report after your top level block diagram