integrate all modules to implement using verilog full Bus$-$based Datapath for RISC$-$V as described in the reference design.

$*$using verilog build this data bath

$*$ you should use structural style; implement the Imm Gen module, and special purpose registers$($IR$,$ A$,$ B$,$ MA$).$

$*$ Datapath input : clock, control signals

$*$ Datapath output: status signals.

$*$ report should includes full documentation of each module with testing and sine wave

$*$ report should include test$-$benches that simulate input coming from control unit.

$*$ report should include your ISA $($subset of risc$-$v ISA with some added features or addressing modes.$)$