Multiprocessor

Question. A 4-?way SMP configuration implements write-?back cache using the MESI (Modified Exclusive Shared Invalid) algorithm for cache coherency. Assume that location 1E0 is not in any cache at the start of the following sequence. Show the state (M, E, S or I) for the line containing location 1E0 in each processor cache and the state in main memory after each operation. Also note any transfers to/from memory if any occur.

For example, if Px has a snoop hit of Py reading a line while it is holding a dirty copy of the line, indicate Px writes lineback, Py reads line under the Memory Transfers column.

a) Processor 0 reads from location 1E0.

b) Processor 0 writes to location 1E0.

c) Processor 1 reads from location 1E0.

d) Processor 2 reads from location 1E0.

e) Processor 1 writes to location 1E0.

f) Processor 3 writes to location 1E0.

Action	P0	P1	P2	P3	Mem	Memory Transfers
P0 reads
P0 writes
P1 reads
P2 reads
P1 writes
P3 writes