Introduction

Extend the single$-$cycle datapath with support for instructions addi, and ori. A remarkable difference between these instructions is the way they convert the $16-$bit immediate value into a $32-$bit value. Add the new logic blocks needed for the instructions, and include a new control signal named ImmExtend that determines how field imm is handled. Each possible value for the new control signal has the following effects:

$0$ Perform a sign extension of field imm. This is the current behavior of the unmodified datapath.

$1$ Perform a zero extension of field imm.

You do not need to download the design on the board. Only simulation results are needed.

Block Diagram

Draw the extended block diagram, including the new exposed control signal. You don't need to represent the control unit. You can leave out all those components of the datapath that remain unmodified, and use labels on your wires to indicate which omitted datapath elements they are connected to$.$

Activation Table

Extend the truth table or activation table for the control unit presented in class to reflect the support for the new instructions. Show only the two new rows in the truth table. The columns should show all control signals, including the new ImmExtend. Use $$don$\text{'}$t cares$($undefined outputs$)$ when possible.

Verilog Implementation

Extend the Verilog implementation of the single$-$cycle datapath to support instructions addi and ori. Submit a file named lab$11.$v on Canvas with the full new datapath implementation ready to be compiled and executed. You may copy and paste the Verilog code of all $.$v$$ files provided on Canvas into your single lab$11.$v file, and then modify it$.$

Apply the modifications to the datapath and the control unit.

Modify the test$-$bench so that it executes the following program:

addi $s$0,$ $zero, $0$x$1$ # $s$0=0$x$00000001$

ori $s$0,$ $s$0,0$x$8000$ # $s$0=0$x$00008001($test no sign extension$)$

addi $s$0,$ $s$0,-1$ # $s$0=0$x$00008000($text sign extension$)$

Implementing this test bench involves modifying module Main to simulate a specific number of execution cycles and the initialization of modules RegisterFile, DataMemory, and InstructionMemory to adopt a suitable initial state when the clear signal is set. Run your code and include the simulation output.

Evaluation

For this lab assignment, you need to submit two files on Canvas:

File lab$11.$pdf or lab$11.$docx containing your diagrams, code, simulation screenshots and any text answers.

File lab$11.$v containing your Verilog code.