It is required to design a synchronous sequential circuit that receives a serial input X that produces 1 when the input sequence is either {101} (i.e., 1 followed by 0 followed by 1) or (011) (i.e., 0 followed by 1 followed by 1) assuming overlapping sequences. The output Z is also a bit stream that produces a 1 only after detecting any of the two sequences. Use an asynchronous reset input to reset the sequential circuit to its initial state. Example: Clock cycle X Z 1 2 3 1 0 1 0 0 0 4 6 1 0 1 1 7 8 9 1 1 0 0 1 1 10 11 12 13 14 15 16 17 18 1 1 0 1 10 0 1 0 1 0 1 0 1 1 0 1 0 0 a) (10 points) Draw a Moore state diagram of the sequential circuit. b) (10 points) Implement your design using a minimal number of D-type flip flops and combinational logic. Specify the K-maps and write the minimal next state and output equations.