iteration of the shown loop. Assume that the data values of the arrays A$,$ B$,$ and C are already in vector registers so there are no loads and stores in this program. $($Hint: Notice that there are $5$ instructions in each thread.$)$ A warp in the GPU consists of $32$ threads, and there are $32$ SIMD lanes in the GPU.

for $($i $=0$; i $<(128*1024)$; i$++)\{$

if $($B$[$i$]<0)\{$

A$[$i$]=$ A$[$i$]*$ C$[$i$]$;

B$[$i$]=$ B$[$i$]+$ D$[$i$]$;

D$[$i$]=$ D$[$i$]+1$;

C$[$i$]=$ C$[$i$]+1$;

$\}\}$

How many warps does it take to execute this program?

B$.$ If the code in part A $($excluding the test of B$[$i$])$ is executed on a vector processor with $32$ vector registers $32$ elements each, and this time the vector processor has to load the vectors from the memory and store them at the end of the loop $($that is after the operations on them have finished executing$).$ The processor has two load$/$store $($L$/$S$)$ units, one add $($ADDVV$/$ADDVI$)$ unit and one multiply $($MULTVV$)$ unit and does not supports chaining.

The vector operations are shown below:

A $=$ A $*$ C;

B $=$ B $+$ D;

D $=$ D $+1$;

C $=$ C $+1$;

The vector code is shown below:

I$0$

LV A

I$1$

LV C

I$2$

MULVV A$,$ A$,$ C

I$3$

LV B

I$4$

LV D

I$5$

ADDVV B$,$ B$,$ D

I$6$

SV A

I$7$

ADDVI D$,$ D$,1$

I$8$

SV B

I$9$

ADDVI C$,$ C$,1$

I$10$

SV D

I$11$

SV C

a$)$ Show how the code will be executed using the table below. Use $3$ squares in the horizontal direction for each operation.

b$)$ Assume that chaining is supported and show how the code can be executed in the table below. Use $3$ squares in the horizontal direction for each operation. When chaining, start the operation that you chain to at least one square to the right under the operation that you chain from. There will be only one chaining path from a functional unit to another functional unit.