Lab 5: 4-bits Universal Binary Counter Objective: The student shall be able to design regular sequential circuits such as counter. en . 9-1 Tasks: (See Textbook code Listing 4.10 and Listing 4.12) Write a VHDL code to design a universal binary counter as shown below. syn.clr load up q* Operation 1 00...00 synchronous clear 0 1 d parallel load 0 1 1 4+1 count up 0 0 1 0 count down 0 0 0 9 pause Assign the I/O ports to the boards I/O pins as follows: Design 1/0 port Board I/O pin Clock (clk) CLK_50M Enable (en) V_SW(O) Count up (up) V_SW(1) Clear (syn_clr) V_BT(0) load V_BT(1) Output (a) G_HEXO Input (d) V_SW(5 downto 2) Synthesize the circuit and upload it to the FPGA prototyping board. Run and verify the operation of counter. Hint: you will need to slow down the main clock frequency (50MHZ) to see the counting operation. Use cycle counter to control the counter operations. Max Count = Max Frequency/Desired Frequency