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Lab$5$: part $3$

Design state machine with Mealy and Moore outputs.

Lab $5-3$ Objective:

Design Sequence detector, state machine with Mealy & Moore $($CO $3,4)$

Design a sequence detector $($solution$)$ with Mealy and Moore outputs, to find$/$detect this sequence of this eight bits$/$states $"011011010"$ The Moore output is active on the last $"0"(8$ th bit$/$state$)$ of the successful sequence.

The Mealy output goes active when the $7$th state$/$bit is $="1",$ and remains active until the last bit $(8$th bit$)="0"($even without a clock transition$).$

The Mealy output "can be$"$ active where the $"^"$ is located $(2$nd to the last state$/$bit$)$: $011011010$

For example: assume input switch $"$A$"$ is generating the sequence; $A,A\frac{,}{A},A\frac{,}{A}$; that would be represented by $11010.$

Note:

When the clock changes the flip$-$flops to another state, the Mealy out goes inactive. The use of the word "ACTIVE". This could mean a high or a low state $($Active High or Active Low$)$

Activities:

Connect to "Global Protect", and then to Campus Computing through Ssasafras.

Draw a state diagram for your sequence detector.

Code state diagram using Verilog $($A$,$ clock are inputs and Mealy and Moore are the outputs$)$

Launch Quartus$/$Questa$/$ModelSim$,$ Compile and then simulate.

Show your waveform result as demo to your instructor.