Lab4. Simplified Microprocessor Design Figure below shows simplified microprocessor diagram having M0, M1, M2 and Cin inputs, one input switch SW1 and also clock input. The SW1 switch serves as asynchronous reset function. Your design should finally implement the following operation: R[2] M0(not M1) Cin The R[2] signal is connected with output "dout" MO M1 M2 Cin Mo M1 M2 Cin| FSM CLR W[2:0] CE[3.0]Datapath SWI RESETw[2:0] CLR CE[3:0] SEL[1:01SEL[1:0] S[2:0] CLK CLK S[2:0] CLK dout Figure. Simplified microprocessor b lock diagram In the above Figure, the "FSM', unt is a finite state machine controller. The logic on "SW1" switch will force the controller to enter its first state. After "SWI becomes logic '0, the finite state machine will proceed forward automatically into the next state after the rising edge of the clock. The major outputs of different states of the controller are control signals for the datapath circuit. (1). Before the final dout result is available, the LED display should be off. (2). After the final dout result is available, the LED display should be off when final result is 0 Otherwise the LED display should be on when the final dout result is '1' Lab4. Simplified Microprocessor Design Figure below shows simplified microprocessor diagram having M0, M1, M2 and Cin inputs, one input switch SW1 and also clock input. The SW1 switch serves as asynchronous reset function. Your design should finally implement the following operation: R[2] M0(not M1) Cin The R[2] signal is connected with output "dout" MO M1 M2 Cin Mo M1 M2 Cin| FSM CLR W[2:0] CE[3.0]Datapath SWI RESETw[2:0] CLR CE[3:0] SEL[1:01SEL[1:0] S[2:0] CLK CLK S[2:0] CLK dout Figure. Simplified microprocessor b lock diagram In the above Figure, the "FSM', unt is a finite state machine controller. The logic on "SW1" switch will force the controller to enter its first state. After "SWI becomes logic '0, the finite state machine will proceed forward automatically into the next state after the rising edge of the clock. The major outputs of different states of the controller are control signals for the datapath circuit. (1). Before the final dout result is available, the LED display should be off. (2). After the final dout result is available, the LED display should be off when final result is 0 Otherwise the LED display should be on when the final dout result is '1