Given a 6 stage pipeline with the following stages:

1. a) FI Fetch Instruction

2. b) DI Decode Instruction

3. c) CO Calculate Operan

4. d) FO Fetch Operand

5. e) EO Execute Operand

6. f) WO Write Operand

Assume all instructions have these 6 stages unless otherwise noted and all 6 stages can be run in parallel. Assume each stage requires 1 clock cycle to complete. What is the pipeline behavior (timing diagram, first 11 clock cycles) for the following instructions in this order and what is the average number of cycles per instruction?

1. orcc

2. st (assume FI, DI, CO, FO,WO)

3. andcc

4. ld (assume FI, DI, CO, FO, WO)

5. Addcc

Discuss why pipelines are utilized in computer processors and architecture ? If the number of instructions in the program is increased to 50 instructions (44 instructions utilize 6 stages in the pipeline, 6 instructions utilize only 5 stages and these occur first in the program), what will the new average CPI be? If the 6 instructions that utilize only 5 stages occur throughout the program of 50 instructions, will the average CPI when compared to the having those 6 instructions at the beginning of the program be the same, go up or go down and why ?

Answer rating: 100% (QA)

Answer I orcc FI I st Is and cc F4 ld Is Addec present 2 DI FI 3 DI FI 4 FO DI FI 5 EO FO DI ... View the full answer