Let$$s say a processor is supposed to support following instructions.

addi, add, sub, and, or$,$ lw$,$ sw$,$ beq, and j

Write a system Verilog module for the datapath of MIPS SCP$.$ The module MUST be named as $$datapath$.$

The skeleton for required module containing the port list of the datapath, as shown in the figure below, is given in file named, $$datapath$.$sv$.$ You are required to complete the module and submit it$.$ After completing the datapath module you can run the testbench provided in file named $$tbDataPath$.$sv$.$

HINT: systemVerilog modules for basic building blocks, needed for constructing the datapath, are given in the textbook. You are supposed to study them on your own and use them as needed.