Figure $1$: Schematic of single$-$cycle MIPS processor

Our model of the single$-$cycle MIPS processor divides the machine into two major units: the control and the datapath. Each unit is constructed from various functional blocks. For example,

as shown in the Figure $1,$ the datapath contains the $32-$bit ALU that you designed in Lab $1\mathrm{.}2,$ the register file, the sign extension logic, and five multiplexers to choose appropriate operands.

$2.$ MIPS Single$-$Cycle Processor

The SystemVerilog single$-$cycle MIPS module is given in Section $7\mathrm{.}6$ of the text. Digital version $($Lab$3\mathrm{.}2-$svCode.rar$)$ of the modules will also be uploaded on LMS$.$ Study the modules until you are familiar with their contents. Look at the mips module, which instantiates two sub$-$modules, controller and datapath. Then take a look at the controller module and its submodules. It contains two sub$-$modules: maindec and aludec. The maindec module produces all control signals except those for the ALU. The aludec module produces the control signal, alucontrol $[\backslash (2$: $0]\backslash ),$ for the ALU. Make sure you thoroughly understand the controller module. Correlate signal names in the System Verilog code with the wires on the schematic.

After you thoroughly understand the controller module, take a look at the datapath System Verilog module. The datapath has quite a few submodules. Make sure you understand why each submodule is there and where each is located on the MIPS single$-$cycle processor schematic. You'll notice that the alu module is not defined. Include your alu module from Lab $1\mathrm{.}2$ into processor. Be sure the module name matches the instance module name $($alu$),$ and make sure the inputs and outputs are in the same order as in they are expected in the datapath module.

The highest$-$level module, top, includes the instruction and data memories as well as the processors. Each of the memories is a $64-$word $\backslash (\backslash$times $32\backslash )-$bit array. The instruction memory needs to contain some initial values representing the program. The test program is given in Figure $7\mathrm{.}60$ of the textbook. Study the program until you understand what it does. Copy the machine language code for the program and stored it in hexfile.dat. $3.$ Testing the single$-$cycle MIPS processor

In this section, you will test the processor you have designed. Simulate your processor with EDA Playground. Be sure to add all of the $.$sv files, including the one containing your ALU. Also add the file hexfile.dat to the test bench as shown in Figure $2.$

Figure $2$: Adding hexfile.dat to the test bench Now run the test bench as given below $($also included in Lab$3\mathrm{.}2-$svCode.rar$)$:

$```$

$//$ Testbench for MIPS processor

$//$ saiful.islam@tedu.edu.tr$,30$ Nov $2024$

$//$

module testbench$()$;

logic clk;

logic reset;

logic $[31$:$0]$ writedata, dataadr;

logic memwrite;

int correctdata $=7$;

$//$ instantiate device to be tested

top dut$($clk$,$ reset, writedata, dataadr, memwrite$)$;

$//$ initialize test

initial

begin

reset ; # $22$; reset ;

end

$//$ generate clock to sequence tests

always

begin

clk ; # $5$; clk ; # $5$;

end

$//$ check that $7$ gets written to address $84$

always@$($negedge clk$)$

begin

if$($memwrite & dataadr $===84)$ begin

$display$("============================")$;

$display$("$Data Address: $\%$d$,$ Correct data: $\%$d$",$ dataadr, correctdata$)$;

if$($writedata $===$ correctdata$)$ begin

$display$("$Simulation succeeded: $")$;

$display$("$Data Address: $\%$d$,$ Data written: $\%$d$",$ dataadr, writedata$)$;

$display$("===========================")$;

$stop;

end else if $($dataadr $!==84|$ writedata $!==$ correctdata$)$ begin

$display$("$Simulation failed"$)$;

$display$("$Data Address: $\%$d$,$ Data written: $\%$d$",$ dataadr, writedata$)$;

$display$("===========================")$;

$stop;

end

end

end

endmodule

$```$

Read the program carefully and note that final sw instruction will write $7$ to the address $84.$ So$,$ if all goes well, the testbench will print "Simulation succeeded." If not, the problem is likely in your ALU or because you didn't properly add all of the files. In this case, you need to recheck that all the modules are added correctly. $4.$ Assignment

Design the MIPS single cycle processor that supports the following instructions: addi, add, sub, and, or$,$ slt$,$ lw$,$ sw$,$ beq, and j$.$

Write your own test program other than the example program given in the textbook. Convert is in machine code and change the hexfile.dat. The following table could be used to compute the $32-$bit machine instructions for the program.