Let us suppose this processor supports not only add, sub, and, or$,$ lw$,$ sw$,$ beq, but also slt$,$ j$.$

Look at Instruction$[20$:$16]$ under the instruction lw$.$ These bits specify the target Write register. $($The control signal RegDst is set to $0$ for this purpose.$)$ However, these bits are also fed into Read Register $2.$ So the output bus Read Data $2$ is set with whatever junk value was in the register already. Explain why this unintended read register is not a problem.

$($Hint: we stop this getting into the ALU, and we don$$t set the memory to be ready for a write.$)$