Li R$8,8$L:Lw R$2,$ R$3,$ R$7$Add R$1,$ R$2,$ R$3$Sub R$7,$ R$1,$ R$3$ LW R$4,10($R$7)$Sw R$4,20($R$1)$Subi R$8,$ R$8,4$BNEQZ R$8,$ LAlso, given the following latencies for each stage:IF: $80$ns$,$ ID: $30$ns$,$ EX: $50$ns$,$ MEM: $85$ns$,$ and WB: $35$nscycles.wigt is the total number of stall cycles needed when running this code on a MIPS Pipelined CPU without data forwarding and the branch resolved in the EX Stage and initialized to be Not Taken. Ignore initial pipeline fillO A$.120.24$O C$.220$ D$.10$O E$.20$