ll Verizon LTE 5:22 PM @ * 86% . Lab 3 Lab 3.pdf CSCI-1510 Lab 3 Be sure to read the below before starting. PART 1 1. The circuit you are to design will output a 1 when 3 of the 4 inputs is not the same as the others In other words, 3 of the inputs are the same. Note this does not say f the inputs are a 1 ora a, just that they are the same 2. You may use a K-map or algebraic manipulation to achieve the optimal circuit 3 Creote a design for this circuit. You may use 4 input NAND (7420) ptes for this circuit as wel as 2 isput NAND gates QNLY. NO OTHER GATES ARE ALLOWED, Le. 7404 To accomplish this, I soggest drawing the circuit out on paper according to the result you got from your K-map and then do the distribution of bubbles to get the NAND equivalent circult. Something to consider NANO gotes are not coscade-able (extendable in the same way as AND and OR from the lost lab) so the extension to mueiple inputs you used for the AND and the OR WLL NOT word for the 4 Simulate your design. This means you will have to build a stimulus file in order to tet the circuit PART 2 1 Design a circuit which generates an even parity bit based on the values of the 3 inputs to the crcuit Information on parity eeneration can be found in section 3.8 of your book 2. Add a new schematic folder to your project. Add a new page and using part 7486, buils the circuit and simulate it. You may need to build a stimulus ile with which to test your circuit. OTE: You may encounter an error that says somethng along the lines of too many parts. you see this error, you need to consider how you can simplify the circuit HINT: Consider an OR gate with all its inputs inverted. The OR gate and the inverters on the input could be replaced by a single gate. Look at the lecture mates for Chapter three for ideas The OR gate and its assoelated inverters on the inpats can be replaced by a single gate CSCI-1510 Lab3 HINT: If you are using a port for every input to every ate. You can eliminate a bunch of parts Dashboard Calendar To Do Notifications Inbox