logic design

1. LOGIC DESIGN WITH DECODERS AND MULTIPLEXERS a) Implement f(x1,x2,x3)=(1,2,3,5) by using a single 3 -to- 8 decoder and minimum number of NAND-2 gates. b) Implement f(x1,x2,x3,x4)=(3,4,6,7,10,13,14) by using a single 4 -to-1 multiplexer and minimum number of NAND-2 gates. c) Implement f(x1,x2,x3,x4)=(0,1,3,7,9,13,14) by using a single 8 -to-1 multiplexer and minimum number of NAND-2 gates. d) Implement a 16-to-1 multiplexer by using 4-to-1 multiplexers. e) Implement a 3-to-8 decoder using minimum number of 2-to-1 multiplexers