Lost in computer architecture!!! Let me know if you have questions!!! THANKS!!

Comp. Parameters:

3 onsider the identical computer o he one in question ut now the sectors are transferre The transfers are done one word at a time by a loop in assembly of the form: rom dis cac e to main memor b using n cessor nvo ed si war transi s n tead i from memory-mapped disk cache address *to main memory * *register increment for address register to main memory */ /* branch back to LW for next iteration for next word *7 loop: LW. SW ADDI.. BNEZ..., Loop Memory mapped locations (the loads above) are not cached by the processor caches. Further, the processor caches use write through for main memory locations. (In a write-through cache, all stores are written to main memory immediately instead of waiting for eviction of that data.). Hence both the loads and stores use the bus. The branch predictor is perfect, and thus there are no stalls from control hazards. What is the total transfer time in software for the sector? 3 onsider the identical computer o he one in question ut now the sectors are transferre The transfers are done one word at a time by a loop in assembly of the form: rom dis cac e to main memor b using n cessor nvo ed si war transi s n tead i from memory-mapped disk cache address *to main memory * *register increment for address register to main memory */ /* branch back to LW for next iteration for next word *7 loop: LW. SW ADDI.. BNEZ..., Loop Memory mapped locations (the loads above) are not cached by the processor caches. Further, the processor caches use write through for main memory locations. (In a write-through cache, all stores are written to main memory immediately instead of waiting for eviction of that data.). Hence both the loads and stores use the bus. The branch predictor is perfect, and thus there are no stalls from control hazards. What is the total transfer time in software for the sector