2. Machine A is based on a single-cycle design with a fixed clock. Consider the following operation times for its major functional units:

• ALU and adders: 200 ps
• Memory Units: 300 ps
• Register file (read or write): 100 ps

Assuming that the control unit, Program Counter (PC) access, multiplexors, sign extension unit, and wires have no delays, determine machine A's clock cycle for executing the following MIPS code:

lw $s1, 100($s2) # $s1 Memory[$s2 + 100]

sw $s3, 100($s4) # Memory[$s4 +100] $s3

add $s1, $s2, $s3 # $s1 $s2 + $s3

beq $s1, $s2, 25 # if ($s1 == $s2) go to PC + 4 + 100

j 2500 # Go to 10000