make a $3-$bit up$-$counter that increments by one normally, and increments by two every other clock cycle, e$.$g$.$ the starting sequence of your counter should be as follows, $000,001,011,100,110,...$ You may use any number of $1-$bit half or full adders, $1-$bit multi$-$function registers, any$-$bit multiplexors and logical gates. There should be an input for the clock and an input clr which resets the counter to $0$ when clr$=1.$ There should be $3-$bits of output which represents the current count and an output tc that is $1$ when the counter is at its terminal count.