Make Verilog behavioral description of a six bit subtractor module, which performs the sub=a-b operation

All data are in 2's complement signed format. No carry in.

Specification:

a) Module name :sub6

b) input signals:

a(6 bit): the input minuend number, in 2 complement format

b(6 bit):the input subtrahend number, in 2 complement format

c) Output signals

sub(6 bits) the subtraction result in 2 complement format;

cout(1bit): the carry out bit