A D flip-flop has a propagation delay from clock to Q of 7 ns. The setup time of the flip-flop is 10 ns, and the hold time is 5 ns. A clock with a period of 50 ns (low until 25 ns, high from 25 to 50 ns, and so on) is fed to the clock input of the flip-flop. Assume a 2-level AND-OR circuitry between the external input signals and the flip-flop inputs. Assume gate delays are between 2 and 4 ns. The flip-flop is positive edge triggered.

(a) Assume the D input equals 0 from t = 0 until t = 10 ns, 1 from 10 until 35, 0 from 35 to 70, and 1 thereafter. Draw timing diagrams illustrating the clock, D, and Q until 100 ns. If outputs cannot be determined (because of not satisfying setup and hold times), indicate it by XX during the region. 

(b) The D input of the flip-flop should not change between ___ ns before the clock edge and ___ ns after the clock edge.

(c) External inputs should not change between ___ ns before the clock edge and ___ ns after the clock edge.