M-bit Two's Complement Addition Boolean Network Example Data to ti tz tz A bit-wide output LSB bit-wide inputs MSB A S 0 1 1 B Network Inputs B Your Design B 1 0 TREET Numerie Interpretation A 0110 +B 0101 S 1011 4u Network Output S 1 1 0 1 Increasing time Global Clock Reset Enable Figure 1: Functional Overview of Two's Complement Adder Assignment Part 1 Develop a Mealy State Graph (SG) for the Two's Complement Design shown in Figure 1. The design should contain a minimum number of states to implement the desired function. Identify the initial state and fully label all states in the diagram. Also label the input(s) and outputof the design. Using this state graph develop an input sequence which will transverse all arcs and nodes of the SG