Question: MIPS can implement the instruction swap rs, rt which swaps the values in registers rs and rt. If we implement this instruction in hardware, the

MIPS can implement the instruction swap rs, rt which swaps the values in registers rs and rt.

If we implement this instruction in hardware, the additional logic will cause the clock period to increase by 15%, thus penalizing all instructions. Under what specific condition could we justify including hardware support for this instruction? Show this mathematically.

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