Show how MIPS can implement the instruction swap rs, rt which swaps the values in registers rs and rt. Consider the case when

a. there is an available register that may be destroyed.

b. there are no registers available for temporary storage.

If we implement this instruction in hardware, the additional logic will cause the clock period to increase by 15%, thus penalizing all instructions. Under what specific condition could we justify including hardware support for this instruction? Show this mathematically.