Modern Digital System Design (ECE 2372)- Project Due Date: 3/26/18 Task (10 points): (1) Approach 1: Implement a 4-to-16-line decoder using the schematic capture feature of Xilinx ISE. On the schematic, add a text that clearly shows your name and eRaider ID (2) Approach 2: Write and compile a 4-to-16-line decoder Verilog gate-level description. (3) Approach 3: Write and compile a 4-to-16-line decoder Verilog behavioral description. (4) Create an appropriate test file to do an exhaustive test. Exhaust all the possible input codes in the following order: 0000 ? 0001 ? 0010 ? 0011 ? ? 1 1 1 1 . For each input code, hold for 20 ns, then change to the next input code (5) Run simulation and generate output waveforms for all three approaches to demonstrate that your design works correctly. Be careful about your design to make sure each output is appropriate for the input. Modern Digital System Design (ECE 2372)- Project Due Date: 3/26/18 Task (10 points): (1) Approach 1: Implement a 4-to-16-line decoder using the schematic capture feature of Xilinx ISE. On the schematic, add a text that clearly shows your name and eRaider ID (2) Approach 2: Write and compile a 4-to-16-line decoder Verilog gate-level description. (3) Approach 3: Write and compile a 4-to-16-line decoder Verilog behavioral description. (4) Create an appropriate test file to do an exhaustive test. Exhaust all the possible input codes in the following order: 0000 ? 0001 ? 0010 ? 0011 ? ? 1 1 1 1 . For each input code, hold for 20 ns, then change to the next input code (5) Run simulation and generate output waveforms for all three approaches to demonstrate that your design works correctly. Be careful about your design to make sure each output is appropriate for the input