modify the code for the stopwatch timer to show : - The number of elapsed seconds on the two rightmost seven segments display (0-59). - The number of elapsed minutes on the two leftmost seven segments display of the Nexys2 board ( 0-59 ) - And do not change the function of the system inputs (clr,go)

(using the software Vivado) the photos show my code to design and implement a stopwatch timer.

? PresentationT.pptx 22 module stopwatchtimer ( 23 input wire clk, 24 input wire [1:0 switches, 25 output wire [3:0] anodes 26 output vire [7:01 sevenseg 27) 28 // Signal Declaration 29//vire [3:0] a, b: 30 wire [7:01 count out: 31 wire new clk; 32 // Instantiate 7-segment LED Display module 33 disp_hex mux disp_unit 34 (.clk(clk), .reset (L'bo), 35 .hex3 (count_out [7:4]) , .hex2 (count_out [3:0])hexl (4'b0000), 36 .hex0 (4 'b0000), 37 .dp_in (4'blolI), .anodes (anodes), .sevenseg (sevenseg)) 38 // instantiate the control counter to lover down the 50MHz to 10Hz 39 cntr cntr unit 40 (.clk(clk), out (new clk)) 41// instantiate the BCD counter 42 bcd counter bcd cntr unit(.cik (new cl)bcd (count_out), .switches (switches)) 43 45 46 47 module disp_hex mux 48 ( 49 input wire clk, reset 50 input wire [3:01 hex3,hex2, hexl, hex0,// hex digits 51 input wire [3:0] dp-in , // decinal points 52 output reg [3:0 anodes,I enable 1-out-of-4 asserted lo 53 output reg [7:01 sevenseg / led segments 54 )2 ? PresentationT.pptx 22 module stopwatchtimer ( 23 input wire clk, 24 input wire [1:0 switches, 25 output wire [3:0] anodes 26 output vire [7:01 sevenseg 27) 28 // Signal Declaration 29//vire [3:0] a, b: 30 wire [7:01 count out: 31 wire new clk; 32 // Instantiate 7-segment LED Display module 33 disp_hex mux disp_unit 34 (.clk(clk), .reset (L'bo), 35 .hex3 (count_out [7:4]) , .hex2 (count_out [3:0])hexl (4'b0000), 36 .hex0 (4 'b0000), 37 .dp_in (4'blolI), .anodes (anodes), .sevenseg (sevenseg)) 38 // instantiate the control counter to lover down the 50MHz to 10Hz 39 cntr cntr unit 40 (.clk(clk), out (new clk)) 41// instantiate the BCD counter 42 bcd counter bcd cntr unit(.cik (new cl)bcd (count_out), .switches (switches)) 43 45 46 47 module disp_hex mux 48 ( 49 input wire clk, reset 50 input wire [3:01 hex3,hex2, hexl, hex0,// hex digits 51 input wire [3:0] dp-in , // decinal points 52 output reg [3:0 anodes,I enable 1-out-of-4 asserted lo 53 output reg [7:01 sevenseg / led segments 54 )2