module multiplier$4$by$3($

input $[2$:$0]$ B$,$

input $[3$:$0]$ A$,$

output $[7$:$0]$ Product

$)$;

wire $[7$:$0]$ P$1,$ P$2,$ P$3,$ P$4,$ P$5,$ P$6$;

$//$ Partial Products

assign P$1=$ A$[3]$ & B$[2$:$0]$;

assign P$2=$ A$[2]$ & B$[2$:$0]$;

assign P$3=$ A$[1]$ & B$[2$:$0]$;

assign P$4=$ A$[0]$ & B$[2$:$0]$;

assign P$5=\{3\text{'}$b$0,$ A$\}$ & B$[2$:$0]$;

assign P$6=\{4\text{'}$b$0,$ B$\}$;

$//$ Full Adders

wire $[7$:$0]$ C;

wire $[7$:$0]$ S;

assign C$[0]=1\text{'}$b$0$;

assign S$[0]=$ P$1$;

assign $\{$C$[1],$ S$[1]\}=$ P$2+$ P$3+$ P$4$;

assign $\{$C$[2],$ S$[2]\}=$ P$5+$ P$6$;

$//$ Final Product

assign Product $=\{$C$[7],$ S$[7$:$3]\}$;

endmodule

Write a test bench for this Verilog module once you have verified your design logically$,$ modify the test bench to have your multiplier conduct the following multiplications, use a table to list your inputs and outputs.

$5$x$3$

$15$x$5$

$9$x$7$

$15$x$7$