Verilog, Mips Question.

-------------------------------------mips_single.sv------------------------------------------------------------------------------------

module testbench();

logic clk; logic reset;

logic [31:0] writedata, dataadr; logic memwrite;

// instantiate device to be tested top dut(clk, reset, writedata, dataadr, memwrite); // initialize test initial begin reset

// generate clock to sequence tests always begin clk

// check results always @(negedge clk) begin if(memwrite) begin if(dataadr === 84 & writedata === 7) begin $display("Simulation succeeded"); $stop; end else if (dataadr !== 80) begin $display("Simulation failed"); $stop; end end end endmodule

module top(input logic clk, reset, output logic [31:0] writedata, dataadr, output logic memwrite);

logic [31:0] pc, instr, readdata; // instantiate processor and memories mips mips(clk, reset, pc, instr, memwrite, dataadr, writedata, readdata); imem imem(pc[7:2], instr); dmem dmem(clk, memwrite, dataadr, writedata, readdata); endmodule

module dmem(input logic clk, we, input logic [31:0] a, wd, output logic [31:0] rd);

logic [31:0] RAM[63:0];

assign rd = RAM[a[31:2]]; // word aligned

always_ff @(posedge clk) if (we) RAM[a[31:2]]

module imem(input logic [5:0] a, output logic [31:0] rd);

logic [31:0] RAM[63:0];

initial $readmemh("testfile.dat",RAM);

assign rd = RAM[a]; // word aligned endmodule

module mips(input logic clk, reset, output logic [31:0] pc, input logic [31:0] instr, output logic memwrite, output logic [31:0] aluout, writedata, input logic [31:0] readdata);

logic memtoreg, alusrc, regdst, regwrite, jump, pcsrc, zero; logic [2:0] alucontrol;

controller c(instr[31:26], instr[5:0], zero, memtoreg, memwrite, pcsrc, alusrc, regdst, regwrite, jump, alucontrol); datapath dp(clk, reset, memtoreg, pcsrc, alusrc, regdst, regwrite, jump, alucontrol, zero, pc, instr, aluout, writedata, readdata); endmodule

module controller(input logic [5:0] op, funct, input logic zero, output logic memtoreg, memwrite, output logic pcsrc, alusrc, output logic regdst, regwrite, output logic jump, output logic [2:0] alucontrol);

logic [1:0] aluop; logic branch;

maindec md(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop); aludec ad(funct, aluop, alucontrol);

assign pcsrc = branch & zero; endmodule

module maindec(input logic [5:0] op, output logic memtoreg, memwrite, output logic branch, alusrc, output logic regdst, regwrite, output logic jump, output logic [1:0] aluop);

logic [8:0] controls;

assign {regwrite, regdst, alusrc, branch, memwrite, memtoreg, jump, aluop} = controls;

always_comb case(op) 6'b000000: controls

module aludec(input logic [5:0] funct, input logic [1:0] aluop, output logic [2:0] alucontrol);

always_comb case(aluop) 2'b00: alucontrol

module datapath(input logic clk, reset, input logic memtoreg, pcsrc, input logic alusrc, regdst, input logic regwrite, jump, input logic [2:0] alucontrol, output logic zero, output logic [31:0] pc, input logic [31:0] instr, output logic [31:0] aluout, writedata, input logic [31:0] readdata);

logic [4:0] writereg; logic [31:0] pcnext, pcnextbr, pcplus4, pcbranch; logic [31:0] signimm, signimmsh; logic [31:0] srca, srcb; logic [31:0] result;

// next PC logic flopr #(32) pcreg(clk, reset, pcnext, pc); adder pcadd1(pc, 32'b100, pcplus4); sl2 immsh(signimm, signimmsh); adder pcadd2(pcplus4, signimmsh, pcbranch); mux2 #(32) pcbrmux(pcplus4, pcbranch, pcsrc, pcnextbr); mux2 #(32) pcmux(pcnextbr, {pcplus4[31:28], instr[25:0], 2'b00}, jump, pcnext);

// register file logic regfile rf(clk, regwrite, instr[25:21], instr[20:16], writereg, result, srca, writedata); mux2 #(5) wrmux(instr[20:16], instr[15:11], regdst, writereg); mux2 #(32) resmux(aluout, readdata, memtoreg, result); signext se(instr[15:0], signimm);

// ALU logic mux2 #(32) srcbmux(writedata, signimm, alusrc, srcb); alu alu(srca, srcb, alucontrol, aluout, zero); endmodule

module regfile(input logic clk, input logic we3, input logic [4:0] ra1, ra2, wa3, input logic [31:0] wd3, output logic [31:0] rd1, rd2);

logic [31:0] rf[31:0];

// three ported register file // read two ports combinationally // write third port on rising edge of clk // register 0 hardwired to 0 // note: for pipelined processor, write third port // on falling edge of clk

always_ff @(posedge clk) if (we3) rf[wa3]

assign rd1 = (ra1 != 0) ? rf[ra1] : 0; assign rd2 = (ra2 != 0) ? rf[ra2] : 0; endmodule

module adder(input logic [31:0] a, b, output logic [31:0] y);

assign y = a + b; endmodule

module sl2(input logic [31:0] a, output logic [31:0] y);

// shift left by 2 assign y = {a[29:0], 2'b00}; endmodule

module signext(input logic [15:0] a, output logic [31:0] y); assign y = {{16{a[15]}}, a}; endmodule

module flopr #(parameter WIDTH = 8) (input logic clk, reset, input logic [WIDTH-1:0] d, output logic [WIDTH-1:0] q);

always_ff @(posedge clk, posedge reset) if (reset) q

module mux2 #(parameter WIDTH = 8) (input logic [WIDTH-1:0] d0, d1, input logic s, output logic [WIDTH-1:0] y);

assign y = s ? d1 : d0; endmodule

module alu(input logic [31:0] a, b, input logic [2:0] alucontrol, output logic [31:0] result, output logic zero);

logic [31:0] condinvb, sum;

assign condinvb = alucontrol[2] ? ~b : b; assign sum = a + condinvb + alucontrol[2];

always_comb case (alucontrol[1:0]) 2'b00: result = a & b; 2'b01: result = a | b; 2'b10: result = sum; 2'b11: result = sum[31]; endcase

assign zero = (result == 32'b0); endmodule

EXTEND SIMPLE MIPS Single CYCLE PROCESSOR Modify the simple MIPS single cycle ("mips_single.sv") System Verilog code to handle one new instruction: branch if not equal (bne). Copy the machine code from the figure below and create a data file named "fibonacci_bne.dat" to test the new bne instruction. Machine code: 20080014 20090000 200d0000 2000001 2000000 214b0001 000a6020 0806020 11090005 016a6020 11a00003 11ae0005 21290001 150dfffa 000c5025 20000001 150dfffb 080c5825 20000000 150dfff8 2002000a ac020054 Assembly code: main: addi $t0,$0, 20 addi $t1, $0, add $t5, 50, add $t6, $0, 1 addi $t2, so, addi $t3, $t2, 1 add $t4, 50, St2 add $t4, $0, St3 loop: beg $t0, $t1, end add $t4, $t3, $t2 beq $t5, se, trans1 beg $t5, $to, trans2 append: addi $t1,$t1, 1 bne $to, $t5, loop store1: or $t2, $e, St4 addi $t5, 50, 1 bne $te, $t5, append store2: or $t3, so, St4 addi $t5, $0, O bne ste, St5, append addi $ve, $0, 10 sw $2, 84(50) Description # set max counter (n+1-20) # fibonacci initialize counter # store selector # store select 1 # $t2