Most of the mid-range commercial computers in use today use some form of the PCI bus to connect to peripherals such as network controllers and disk controllers. The first two generations of PCI were built on a parallel bus implementation, with the ability of doing half duplex (one direction) 64 bit transfers at speeds up to 133 MHz (higher clock rates were specified but not widely deployed). These parallel bus implementations have now been replaced by PCI Express (PCIe), a serial bus implementation which, in version 1, used a full duplex point-to-point data rate of 2.5 Gbit per link, in both directions with its initial deployment. PCIe devices can be connected across multiple links if they require large bandwidth (e.g. graphics controllers often use 16x PCIe connections). What is the maximum bandwidth (Bytes/Second) of the 64 bit, 133 MHz PCI parallel bus implementation ? What is the maximum full duplex bandwidth of a 4x PCIe version 1.x serial bus implementation ? (PCIe is now widely released in version 4.x and beginning to be released in version 5.0., but we want an answer here for version 1)

Answer rating: 100% (QA)

To calculate the maximum bandwidth of the 64bit 133 MHz PCI parallel bus implementation we need to c... View the full answer