Question: MSU Denver, CS CS 2 4 0 0 : Computer Organization 2 Dr . Weiying Zhu Homework 1 ( Total Points: 8 0 ) ,

MSU Denver, CS CS 2400: Computer Organization 2 Dr. Weiying Zhu
Homework 1(Total Points: 80), Due Date* : 11:59pm 01/26/2024, Cutoff Deadline** : 11:59pm 01/28/2024
* Late penalty will apply for past-due late submission; ** Submission will NOT be accepted after the cutoff deadline
Relevant Topics: Discussed in the lectures/classes before or on the Due Date.
Submission: Upload and submit your solutions in Canvas. Only ONE attempt is allowed for each student. Please try your best to
TYPE your solutions. If your solutions are in hand-written, please SCAN it into a .pdf file. Then upload the file and submit your
homework in Canvas. (NO Paper/Hardcopy or Email submission please!)
Please 1) organize your solutions to the problems in the same order given in the assignment,
2) include enough details to show your work for problems A and D to receive credits for those two problems,
3) include your First Name and Last Name on the page(s) that you upload & submit in Canvas,
4) NAME your HW file as "HW<#>", e.g., HW1SmithAlice.pdf for HW1.
Grading: I will grade it in Adobe Acrobat with corrections and post the graded work with corrections in Canvas for everyone who
submits it.
Problem A. On an ARM processor, determine the values of four condition flags in APSR after an arithmetic operation is executed in
each case (assuming that S-bit is set). The addition or subtraction must be performed in HEX or BIN and can NOT be performed in
DEC since those numbers represent signed OR unsigned values (These instructions are NOT executed one after the other one; instead,
each instruction starts with the initial conditions given in the statement.)
(a)0x92394103+0xA04230C8
(b)0x123456780xEDCBA988(optional,10 extra bonus points)
Problem B. In each of the following MOV or MVN instruction, identify whether the use of the immediate value is VALID or INVALID.
(a) MOV R1, #0xD017
(b) MOVW R1, #0xE689
(c) MOV R1, #0xAC5
(d) MVN R1, #0xAC5
(e) MVN R1, #996
(f) MVN R1, #0x9B000000
(g) MOV R1, #0xF300F300
(h) MOV R1, #0x1357CDEF
Problem C: On an ARM processor, assuming that [N-bit]=0,[Z-bit]=0,[C-bit]=1,[V-bit]=1, predict whether each of the following
branch instruction is going to make the flow of control branch to the instruction labeled by NEXT (i.e., YES or NO).(These instructions
are NOT executed one after the other one; instead, each instruction starts with the initial conditions given in the statement.)
(a) BLS NEXT
(b) BNE NEXT
(c) BLE NEXT
(d) BVC NEXT
Problem D. On an ARMv7-M or ARMv8-M processor, assuming that [R1]=0x010E0C2D,[R2]=0xFDB97531,[R3]=0x0000000C,
[N-bit]=1,[Z-bit]=0,[C-bit]=0,[V-bit]=1, predict the 32-bit [R1],[N-bit],[Z-bit], and [C-bit] after an ARM instruction is executed
in EACH case. (These instructions are NOT executed one after the other; instead, each instruction starts with the initial conditions given
in the statement.)
(a) MOVS R1, #0xFAB
(b) MVNS R1, #0x2FC
(c) MVNS R1, R2, LSL R3
(d) LSRS R1, R2, R3
(e) MVNS R1, R2

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