Question: MSU Denver, CS CS 2 4 0 0 : Computer Organization 2 Dr . Weiying Zhu Homework 1 ( Total Points: 8 0 ) ,
MSU Denver, CS CS : Computer Organization Dr Weiying Zhu
Homework Total Points: Due Date : :pm Cutoff Deadline : :pm
Late penalty will apply for pastdue late submission; Submission will NOT be accepted after the cutoff deadline
Relevant Topics: Discussed in the lecturesclasses before or on the Due Date.
Submission: Upload and submit your solutions in Canvas. Only ONE attempt is allowed for each student. Please try your best to
TYPE your solutions. If your solutions are in handwritten, please SCAN it into a pdf file. Then upload the file and submit your
homework in Canvas. NO PaperHardcopy or Email submission please!
Please organize your solutions to the problems in the same order given in the assignment,
include enough details to show your work for problems A and D to receive credits for those two problems,
include your First Name and Last Name on the pages that you upload & submit in Canvas,
NAME your HW file as HW# eg HWSmithAlice.pdf for HW
Grading: I will grade it in Adobe Acrobat with corrections and post the graded work with corrections in Canvas for everyone who
submits it
Problem A On an ARM processor, determine the values of four condition flags in APSR after an arithmetic operation is executed in
each case assuming that Sbit is set The addition or subtraction must be performed in HEX or BIN and can NOT be performed in
DEC since those numbers represent signed OR unsigned values These instructions are NOT executed one after the other one; instead,
each instruction starts with the initial conditions given in the statement.
axxAC
bxxEDCBAoptional extra bonus points
Problem B In each of the following MOV or MVN instruction, identify whether the use of the immediate value is VALID or INVALID.
a MOV R #xD
b MOVW R #xE
c MOV R #xAC
d MVN R #xAC
e MVN R #
f MVN R #xB
g MOV R #xFF
h MOV R #xCDEF
Problem C: On an ARM processor, assuming that NbitZbitCbitVbit predict whether each of the following
branch instruction is going to make the flow of control branch to the instruction labeled by NEXT ie YES or NOThese instructions
are NOT executed one after the other one; instead, each instruction starts with the initial conditions given in the statement.
a BLS NEXT
b BNE NEXT
c BLE NEXT
d BVC NEXT
Problem D On an ARMvM or ARMvM processor, assuming that RxECDRxFDBRxC
NbitZbitCbitVbit predict the bit RNbitZbit and Cbit after an ARM instruction is executed
in EACH case. These instructions are NOT executed one after the other; instead, each instruction starts with the initial conditions given
in the statement.
a MOVS R #xFAB
b MVNS R #xFC
c MVNS R R LSL R
d LSRS R R R
e MVNS R R
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