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1. Write the synthesize Verilog code for a 32-bit register in behavioral style. Theregister supports read and write accesses. The content of the register is always available at the output portrdata. The register performs one write per cycle. This register has only one control calledwrite_enable. Whenwrite_enableis high, a write takes place on the next positive edge of the clockclkusing input datawdata. When an active low resetrstis asserted, the register is initialized to 0. Provide the source code for register and testbench to validate it in behavioral Verilog. (50 points)

2. Consider the following C-code fragment:

for (i=0; i<100; i++)

a[i] = b[i] - d[i];

Assume that - a, b, and d are arrays of 32-bit words,

The machine code for this fragment is stored in memory starting from location 00000100 Hex.

a- Convert this code to MIPS. You must provide the numeric offset for each branch or jump instruction that you use. (20 points)

b- Assume that theCPIsfor MIPS instructions are as listed below: a.lw: 5 cycles b. R-type,addi,sw, and other immediate Arithmetic instruction : 4 Cycles c.beq,bne, and j: 3 cycles How many clock cycles does it take to execute the C-code fragment? (20 points)

c- Assume that this code is executed by a 1.6GHzsystem. What is thecpuexecution time for the code? (10 points)