Need help with 2 questions please!

HW02 Q4. How many S-bit pointers can be stored by a register with T latches, where T>S? Express your answer using ceiling or floor notation. z = HW02 Q1. Let the worst case propagation delay for a NOT gate be 10 ns (nanoseconds, 10-9 sec), be 20 ns for 2-input logic gates, be 24 ns for 3-input logic gates, and be 28 ns for 4- input logic gates. Consider the Boolean SOP expression a'b'c + a'b' + ac' + abc' and its simplified form z = a'b' + ac' Assume that only the logic signal inputs a, b, and c are available, meaning that if, for example, a'is needed as an input to the function then it must be computed from the logic signal a using a NOT gate. How much less is the worst case propagation delay for the simplified form than for the original expression