need help with creating top level and testbench VHDL codes

1. Control ALU without feedback: this circuit requires you to create a FSM that causes your ALU to perform all of its operations at least once. 1. List all of the inputs needed by the ALU 2. List all of the control signals that will be generated by the FSM 3. Create both circuits in VHDL, and use both as components in a top-level system. 4. Create a testbench that interfaces with your top-level and causes your FSM to go through all of its states. 1. Control ALU without feedback: this circuit requires you to create a FSM that causes your ALU to perform all of its operations at least once. 1. List all of the inputs needed by the ALU 2. List all of the control signals that will be generated by the FSM 3. Create both circuits in VHDL, and use both as components in a top-level system. 4. Create a testbench that interfaces with your top-level and causes your FSM to go through all of its states