Need this implemented in System Verilog.

Data Inputs: A$7,$ A$6,$ A$5,$ A$4,$ A$3,$ A$2,$ A$1,$ A$0($SW$7...$ SW$0)$

Control Inputs: OnOff $($Key$2),$ Clear $($Key$0),$ Set$($Key$1)$

Outputs: A$7$out, A$6$out, A$5$out, A$4$out, A$3$out, A$2$out, A$1$out, A$0$out $($LEDR$7...$LEDR$0)$

Outputs: B$2$out, B$1$out, B$0$out $($HEX$0)$

Outputs: Y$7,$ Y$6,$ Y$5,$ Y$4,$ Y$3,$ Y$2,$ Y$1,$ Y$0($LEDG$7...$LEDG$0)$