Need VHDL code for procedure with comments please

1. Requirement A combinational network accepts a 3-bit binary number(x) and generates a binary number(y) equal to 3x+9. Design, implement and test the below circuit using Xilinx: X1 y = 3x + 9 YO Y1 Y2 Y3 Y4 X2 Note: xy: positive and integer 2. Pre-lab Draw the truth table, develop K-maps and derive the equation for the output (assume XO, X1, X2 inputs and YO - Y4 outputs) 3. Procedure a. Design the circuit in VHDL. Inputs and outputs are std_logic. Behavioral architecture b. Synthesize your design and assure that there are no errors or warnings. c. Create a test bench for your code. 1. Requirement A combinational network accepts a 3-bit binary number(x) and generates a binary number(y) equal to 3x+9. Design, implement and test the below circuit using Xilinx: X1 y = 3x + 9 YO Y1 Y2 Y3 Y4 X2 Note: xy: positive and integer 2. Pre-lab Draw the truth table, develop K-maps and derive the equation for the output (assume XO, X1, X2 inputs and YO - Y4 outputs) 3. Procedure a. Design the circuit in VHDL. Inputs and outputs are std_logic. Behavioral architecture b. Synthesize your design and assure that there are no errors or warnings. c. Create a test bench for your code