Question: Negative edge SR - latch a . Derive the Negative edge D - FF using NAND - gate SR - latch diagram ( no inverters

Negative edge SR-latch
a. Derive the Negative edge D-FF using NAND-gate SR-latch diagram (no inverters or equivalent permitted)
b. Assume the delay through each NAND gate is 2 ns .
c. Draw the simulation diagram showing both rising edge and falling edge clocks (Assume
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Negative edge SR - latch a . Derive the Negative

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