$1)$ Negative edge SR$-$latch

a$.$ Derive the Negative edge D$-$FF using NAND$-$gate SR$-$latch diagram $($no inverters or equivalent permitted$)$

b$.$ Assume the delay through each NAND gate is $2$ ns $.$

c$.$ Draw the simulation diagram showing both rising edge and falling edge clocks $($Assume

$2)$ Ranging detection circuit:

a$.$ Design a four$-$input detector circuit whose output is equal to $1$ when the number of $1\text{'}$s modulo $3$ is $0.$

b$.$ Using exclusive OR gates, derive a four$-$bit binary to gray code converter.

c$.$ Using a case statement, write the pseudo code for the circuit in part $($b$).$ You may use behavioral Verilog.