Note: All code should be typea Shift registers, 4 pts] Write the VHDL code (libraries, entity, architecture) for an N-bit "super"-register that responds to 3 control bits, A2A1A. N should be defined as an entity, as a generic with a default value of 8. The operation of the register is as follows: A2AiAeAction 00 0 Hold state 0 0 Shift lef 00Shift right 01Synchronous clear (set all values to zero 100Synchronous set (set all values to one) 1 0 Count u 110 Count down 1 1 1Parallel load When shifting left, input bit LSI should be put in the LSB; when shifting right, input bit RSI should be put into the MSB. The register has an N-bit input, D, and n N-bit ouput, QThe block diagram of the super register is shown below. RSI LSI 3 Note: All code should be typea Shift registers, 4 pts] Write the VHDL code (libraries, entity, architecture) for an N-bit "super"-register that responds to 3 control bits, A2A1A. N should be defined as an entity, as a generic with a default value of 8. The operation of the register is as follows: A2AiAeAction 00 0 Hold state 0 0 Shift lef 00Shift right 01Synchronous clear (set all values to zero 100Synchronous set (set all values to one) 1 0 Count u 110 Count down 1 1 1Parallel load When shifting left, input bit LSI should be put in the LSB; when shifting right, input bit RSI should be put into the MSB. The register has an N-bit input, D, and n N-bit ouput, QThe block diagram of the super register is shown below. RSI LSI 3