Note: For this homework assume the main memory has 16 addresses such that address I has data Di, where 0

Question 3. [30 points]

For a processor having two caches, a level 1 cache (i.e., L1 cache) which is direct-mapped; and a level 2 cache (i.e., L2 cache), which is 2-way set associative, show the placement in the caches and hit/miss for each of the following address requests. You must show the tag and index for each.

0, 4, 12, 0, 2, 3, 6, 13, 1, 15, 8, 0, 2, 3, 15

Assume warm cache start with the following cache status: (Note: the index and tag field are left blank on purpose) and also assume addresses are real Tag Data D8 Index Tag Data D8 D6 D11 D2 D3 D6 D11 L1 L2