$1.$ A cache has the following parameters: b$,$ block size given in numbers of

words; S$,$ number of sets; N$,$ number of ways; and A$,$ number of address

bits. $($a$)$ In terms of the parameters described, what is the cache capacity,

C$?$

$($b$)$ In terms of the parameters described, what is the total number of bits

required to store the tags?

$($c$)$ What are S and N for a fully associative cache of capacity C words

with block size b $?$

$($d$)$ What is S for a direct mapped cache of size C words and block size b

$?$

$2.$ A $16-$word cache has the parameters given in problem $1.$ Consider the

following repeating sequence of $1$w addresses $($given in hexadecimal$)$:

$4044484$C $7074787$C $8084888$C $9094989$C $048$ C $1014181$C $20$

Assuming least recently used $($LRU$)$ replacement for associative caches,

determine the effective miss rate if the sequence is input to the following caches, ignoring startup effects $($i$.$e$.,$ compulsory misses$).($a$)$ direct

mapped cache, S $=16,$ b $=1$ word

$($b$)$ fully associative cache, N $=16,$ b $=1$ word

$($c$)$ two$-$way set associative cache, S $=8,$ b $=1$ word

$($d$)$ direct mapped cache, S $=8,$ b $=2$ words

$3.$ Assume that main memory accesses take $70$ ns and that memory accesses

are $36\%$ of all instructions. The following table shows data for L$1$ caches

attached to each of two processors, P$1$ and P$2.$

L$1$ Size L$1$ Miss Rate L$1$ Hit Time

P$12$ KB $8\mathrm{.}0\%0\mathrm{.}66$ ns

P$24$ KB $6\mathrm{.}0\%0\mathrm{.}90$ ns

$$ Assuming that the L$1$ hit time determines the cycle times for P$1$ and

P$2,$ what are their respective clock rates?

$$ What is the Average Memory Access Time for P$1$ and P$2?$

$$ Assuming a base CPI of $1\mathrm{.}0$ without any memory stalls, what is the

total CPI for P$1$ and P$2?$ Which processor is faster? $($When we say a

$$base CPI of $1\mathrm{.}0,$ we mean that instructions complete in one cycle,

unless either the instruction access or the data access causes a cache

miss.$)$ For the next three problems, we will consider the addition of

an L$2$ cache to P$1$ to presumably make up for its limited L$1$ cache

capacity. Use the L$1$ cache capacities and hit times from the previous

table when solving these problems. The L$2$ miss rate indicated is its

local miss rate.

L$2$ Size L$2$ Miss Rate L$2$ Hit Time

$1$MB $95\%5\mathrm{.}62$ ns

$$ What is the AMAT for P$1$ with the addition of an L$2$ cache? Is the

AMAT better or worse with the L$2$ cache?

$$ Assuming a base CPI of $1\mathrm{.}0$ without any memory stalls, what is the

total CPI for P$1$ with the addition of an L$2$ cache?

$$ What would the L$2$ miss rate need to be in order for P$1$ with an L$2$

cache to be faster than P$1$ without an L$2$ cache?

$$ What would the L$2$ miss rate need to be in order for P$1$ with an L$2$

cache to be faster than P$2$ without an L$2$ cache?