Question: NOTE TO EXPERTS: PLEASE DON'T ATTEMPT THIS QUESTION IF YOU ARE NOT EXPERT AT MIPS ASSEMBLY LANGUAGE In a MIPS processor, I/O address space 0xffff0000

NOTE TO EXPERTS: PLEASE DON'T ATTEMPT THIS QUESTION IF YOU ARE NOT EXPERT AT MIPS ASSEMBLY LANGUAGE

In a MIPS processor, I/O address space 0xffff0000 to 0xffffffff is reserved for memory-mapped I/O. Assuming that an I/O device needs 1, 1, and 6 32-bit words for control, status and data registers respectively. How many I/O devices this processor can support?

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