Objective: To implement a Verilog gate level model for $32-$bit barrel shifter.

Outcome: Gate level implementation for the following components.

SHIFT$32$

Complete gate level description of following components in barrel$\_$shifter.v file.

SHIFT$32\_$L

SHIFT$32\_$R

BARREL$\_$SHIFTER$32$

SHIFT$32$

Compile entire Project and simulate following modules in ModelSim simulator.

BARREL$\_$SHIFTER$32\_$TB

Observe corresponding outcomes on waveform windows and fix any issue.

Each testbench will generate corresponding output file.

OUTPUT$/$barret$\_$shifter$\_$tb$.$out

This will also generate pass$/$total statistics on console.

This should match with corresponding golden output file in CS$147-$Project$03/$GOLDEN$/$ directory.

barret$\_$shifter$\_$tb$.$out.golden

Add more testing in these testbenches to make sure outcome is correct.

$//$ Name: barrel$\_$shifter.v

$//$ Module: SHIFT$32\_$L $,$ SHIFT$32\_$R$,$ SHIFT$32$

$//$ Notes: $32-$bit barrel shifter

include $"$prj$\_$definition.v$"$

$//32-$bit shift amount shifter

module SHIFT$32($Y$,$D$,$S$,$ LnR$)$;

$//$ output list

output $[31$:$0]$ Y;

$//$ input list

input $[31$:$0]$ D;

input $[31$:$0]$ S;

input LnR;

$//$ TBD

endmodule

$//$ Shift with control L or R shift

module BARREL$\_$SHIFTER$32($Y$,$D$,$S$,$ LnR$)$;

$//$ output list

output $[31$:$0]$ Y;

$//$ input list

input $[31$:$0]$ D;

input $[4$:$0]$ S;

input LnR;

$//$ TBD

endmodule

$//$ Right shifter

module SHIFT$32\_$R$($Y$,$D$,$S$)$;

$//$ output list

output $[31$:$0]$ Y;