Question: On an ARMv7-M processor, assuming that [R1] = 0x7F0E0C2D, [R2] = 0x2468ACE0, [R3] = 0x1048B3C5, [N-bit] = 0, [Z-bit] = 0, [C-bit] = 1, [V-bit]

On an ARMv7-M processor, assuming that [R1] = 0x7F0E0C2D, [R2] = 0x2468ACE0, [R3] = 0x1048B3C5, [N-bit] = 0, [Z-bit] = 0, [C-bit] = 1, [V-bit] = 0, predict the 32-bit [R1] and all four condition flags in APSR after an ARM arithmetic/logical instruction is executed in EACH case.

ADDW R1, R2, #0xF1B

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