Problem B. On an ARMv7-M processor, assuming that [R1] = 0x7F0E0C2D, [R2] = 0x2468ACEO, [R3] = 0x1048B3C5, [N-bit) = 0, [Z-bit) = 0, [C-bit) = 1, [V-bit) = 0, predict the 32-bit [R1] and all four condition flags in APSR after an ARM arithmetic/logical instruction is executed in EACH case. (These instructions are NOT executed one after the other one; instead, each instruction starts with the initial conditions given in the statement.) (a) ADCS R1, R3, ROR #0x18 (b) ADDW R1, R2, #0xF1B (c) SUBS R1, R2, R3 (d) RSBS R1, R2, #0x12 (e) SBCS R1,R3, LSL #12 (f) EORS R1, R2, R3, LSR #4 (g) BICS R1, R2, R3, RRX (h) ANDS R1, R2, ASR #28 (i) ORR R1, R2, R3 (j) ORN R1, R2, #OxB600B600 Problem B. On an ARMv7-M processor, assuming that [R1] = 0x7F0E0C2D, [R2] = 0x2468ACEO, [R3] = 0x1048B3C5, [N-bit) = 0, [Z-bit) = 0, [C-bit) = 1, [V-bit) = 0, predict the 32-bit [R1] and all four condition flags in APSR after an ARM arithmetic/logical instruction is executed in EACH case. (These instructions are NOT executed one after the other one; instead, each instruction starts with the initial conditions given in the statement.) (a) ADCS R1, R3, ROR #0x18 (b) ADDW R1, R2, #0xF1B (c) SUBS R1, R2, R3 (d) RSBS R1, R2, #0x12 (e) SBCS R1,R3, LSL #12 (f) EORS R1, R2, R3, LSR #4 (g) BICS R1, R2, R3, RRX (h) ANDS R1, R2, ASR #28 (i) ORR R1, R2, R3 (j) ORN R1, R2, #OxB600B600