Only anlayse the code in red please

Assume the $5-$stage pipeline machine support $2-$read ports and $1$ write$-$port. Assume there is no implicit bypass forwarding of execution result to register read. Further, assume there is only $1$ memory unit which does not allow read and write the memory at the same time.

What is the average CPI for executing this code segment.

Please describe$/$create a table for the pipeline stages