Question 1: Machine code for four instruction set architechtures.

Descriptions

Be sure to clearly state any assumptions that you make in solving these problems. Use the notation used in lecture and the handouts when referring to fields in a pipeline stage register. Carefully state the units of any answers you give. The first two problems in this set are a continuation of Questions 1-4 on Homework Set #1. Refer to the architecture descriptions there. Assume that for all four instruction set architectures: The opcode is always six bits. All data operands are eight bytes (that is, 64 bits). All memory addresses are eighteen bits, using direct addressing. (That is, an 18-bit fiecld in the machine code is a direct pointer to a data memory with 2" bytes.) In the data memory, assume A is at address Ox 1E500, B is at OXIE508, C is at Ox1E510, and D is at OXIE518. Each architecture uses a fixed length instruction set (that is, every instruction used by that architecture has the same integer number of bytes). Machine code for the four instruction set architectures Question 1. (a) How many bytes are needed for each instruction for the accumulator architecture? Show how you would arrange the fields for the instructions STORE A and MUL D. Show the resulting machine code for these instructions in hexadecimal, assuming STORE has the opcode Ox01 and MUL has the opcode Ox03. (b) How many bytes are needed for each instruction for the stack architecture? Show how you would arrange the fields for the instructions PUSH A and MUL. Show the resulting machine code for these instructions in hexadecimal, assuming PUSH has the opcode Ox00 and ADD has the opcode Ox02. Mul opcode = Ox03 (c) How many bytes are needed for each instruction for the two-address load-store architecture? Assume it has 32 working registers in the register file. Show how you would arrange the fields for the instructions STORE A, RI and MUL R2, R1. Show the resulting machine code for these instructions in hexadecimal, assuming STORE has the opcode 0x01 and MUL has the opcode Ox03. (d) How many bytes are needed for each instruction for the three-address memory-memory architecture? Show how you would arrange the fields for the instruction ADD A, A, D. Show the resulting machine code for this instructions in hexadecimal, assuming ADD has the opcode Ox02. Comparing the four instruction set architectures Question 2. Please base your answers on the code in the posted solutions (rather than on the code you turned in). Make a table to compare the four architectures, showing: [Note which architectures result in (a) The code size in bytes needed to implement A = A+ A* D. less demand for program memory.] HOMEWORK POLICY: While it is fine to discuss possible approaches to these problems with fellow students, you must work independently when you actually sit down to work out the answers. Homework is due at the beginning of lecture on the due date. Please show your work, and carefully state any assumptions you make in solving these problems. The first four questions consider four architecture styles. (You can find more information about these architectures in Appendix A, Section A.2 of the text. Note that the MIPS is a three-address load-store architecture, yet another style.) All four machines are non-pipelined, with a perfect memory system. (Then, each instruction requires exactly one clock cycle.) For each machine, you will write assembly language code to do the computation A=A+A*D. Write your code efficiently, and comment each line with a register transfer level (RTL) description of the function of that line. /Question 1. An accumulator architecture An accumulator architecture is simple but still used on many microcontrollers. Every math operation uses a special working register called the accumulator as one of its two inputs, and puts its result back into the accumulator. Suppose that the accumulator architccture uses a 100 ns clock cycle and has the following instructions: Reads the memory at the given address and puts the data in the LOAD accumulator: Example: LOADA ;ACC+Mem[A] Copies the data from the accumulator, writing it to memory at the given address. Example: STORE A ; Mem[A] ACC Reads the memory at the given address, adds the data read to the data in the accumulator, and writes the result in the accumulator. Example: ADD A Reads the memory at the given address, adds the data read to the data in the accumulator, and writes the result in the accumulator. Example: MUL A STORE ADD : ACC E ACC + Mem [A] MUL ; ACC E ACC * Mem [A] Write assembly language code for the high-level code fragment A=A+A*D on the accumulator architecture. Include RTL comments, What is the IC for your code? How long will it take to run? Question 2. A stack architecture A stack architecture is used in many calculators. It uses a collection of registers called the stack, with the restriction that you access only the piece of data on the top of the stack. When you push a new data value onto the stack, it goes on top (TOS), and everything else gets pushed down - like the "pop-up" plate dispensers in a cafeteria. When you pop a data value off of the stack, it comes off the top, and everything else moves up the stack. Math operations pop the top two pieces of data off the stack, do the math, and push the answer back on the stack. Suppose that the stack architecture has a 120 ns clock cycle, and the following instructions: Reads the memory at the given address and places the data onto the top of the stack. Example: PUSHA ; TOS E Mem[A] PUSH . Example ADD R2, RI Regs (R2j E Regs [R2] + Regs [RI] Adds the data in the two registers indicated together, and puts the result in the register indicaled by reg addrl>. Example: MUL. R2, RI : Regs (R2] E Regs [R2] * Regs (RI] LOAD reg addr, mem addr> STORE ADD , reg addr2> MUL reg addr l>, reg addr2 Write assembly language code for the high-level code fragment A-A+AD on the two-address load-store architecture. Do not use more memory locations or registers than you need. Include RTL comments. What is the IC for your code? How long will it take to run? Question 4. A three-address memory-memory architecture A memory-memory architecture works dircectly on data in memory, rather than using any kind of working registers. Suppose the three-address memory-memory architecture has a 400 ns clock cycle time, and the following instructions: Adds the data read from memory addresses 2 and 3, and writes result to memory address 1. Example: ADD A, B, C ADD , , Mem [A] Mem [B] + Mem [C] Multiplies the data read from memory addresses 2 and 3, and writes result to memory address 1. Example: MUL A, B, C MUL , , : Mem [A] E Mem [B] * Mem [C] Write assembly language code for the high-level code fragment A=A+A*D on the two-address load-store architecture. Include RTL comments. Do not use more memory locations than you need. What is the IC for your code? How long will it take to run? ACCUMULATOR ARCHITECTURE STACK ARCHITECTURE data mem date men PUSH POP stoRE TOS TOS-2 ALU LOAD > AcC STACK TWO-ADDRESS LOAD/STORE ARCH THREE-ADPRESS MEH-MEM ARCH. |Write port (c) data data addr A write port (A) LOAD mem addr C mem reg file STORE read port (6) real port CA) read grt read PoB) ALU