only need question 2 part c, and question 3.

2. Design a counter (shown in Figure 2) to count through the sequence 00, 01, 11, 10, 00, Note that there is only a single input (CLK) and two active-high outputs (Q1 and Q0). (To start the counter at a known value, use the pre-sets and pre-clears of the two flipflops.) a. Make a next-state truth table. The inputs for this table are Q1 and Q0; the outputs are Q1+ and Q0+. b. Using D-flip-flops, determine the next state equations for Di = Qi + = f(Q1,Q0). Use K-maps, if necessary, for each Di to get MSOP or MPOS equations. Note: There will be two 2-input K-Maps. c. Design the required counter circuit in Quartus (called Lab3_2bit_Cnt). (I suggest that you do it first on paper, but this is not required and will not be submitted.) I suggest that you use one of the below two possible D- flip-flops available in Quartus. i. Use others | maxplus2 | 7474 for the left item in Figure 3. ii. Use primitives | storage | dff for the right item in Figure 3. d. Simulate the circuit and, as always, annotate this simulation. Verify that your design counts as required with each rising CLK edge. 3. Create a component in Quartus for 7-segment Decoder!