ONLY USING VHDL PLEASE DO NOT USE VERILOG: In the block diagram given below inputs are fed into the first row of ALU blocks as shown. Each of the inputs to the ALUs are 8-bit wide. Program / Configure the ALUs in such a way that the ALU(1,1) performs a NAND, ALU(1.2) performs a NOR, ALU(1,3) performs an AND and ALU(1,4) performs an OR Program the ALUs in the second row with the following operations: ALU(2.1) performs an Addition, ALU(22) performs a Logical Right Shift, ALU(2,3) performs an Arithmetic Right Shift, and ALU(24) performs a Subtraction. For this question, use the MUX based interconnect as shown in the block diagram. The codes must be properly commented. (5 +55+5) PLEASE INCLUDE VHDL CODE AND ALSO THE TEST BENCH CODE. ALU11 MUX INTERCONNECT REPEATS ALU, OUTPUT BUS ONLY USING VHDL PLEASE DO NOT USE VERILOG: In the block diagram given below inputs are fed into the first row of ALU blocks as shown. Each of the inputs to the ALUs are 8-bit wide. Program / Configure the ALUs in such a way that the ALU(1,1) performs a NAND, ALU(1.2) performs a NOR, ALU(1,3) performs an AND and ALU(1,4) performs an OR Program the ALUs in the second row with the following operations: ALU(2.1) performs an Addition, ALU(22) performs a Logical Right Shift, ALU(2,3) performs an Arithmetic Right Shift, and ALU(24) performs a Subtraction. For this question, use the MUX based interconnect as shown in the block diagram. The codes must be properly commented. (5 +55+5) PLEASE INCLUDE VHDL CODE AND ALSO THE TEST BENCH CODE. ALU11 MUX INTERCONNECT REPEATS ALU, OUTPUT BUS