Parameters

Your goal is to determine the minimal parameterization for a BTB $($Figure $1)$ such that the performance of a fixed branch penalty configuration is matched. The properties of a common baseline system are as follows:

CPI of the common CPU is $1$ when there are no stalls.

The branch penalty of the $($no BTB$)$ baseline architecture is $2$ cycles.

Conditional branch frequency is $15\%.$

The additional known properties of the proposed BTB are:

BTB hit rate $85\%$

BTB accuracy of $80\%$

Buffer miss penalty of $3$ cycles

Branch miss prediction penalty of $4$ cycles

Figure $1$ summarizes the basic sequencing of BTB tests.

Question

On a BTB hit, consider the impact of storing either an address or the target instruction and address under the following conditions:

the address of the instruction for branch taken. This incurs a cost of one clock cycle before the correct instruction can be fetched.

both the address and target instruction are stored at the BTB$.$ This implies that on a BTB hit the fetch cycle can be skipped and execution commences at 'decode'.

What is the speedup relative to the no BTB scenario for each of the BTB configurations assuming that all other BTB properties remain the same? Is there any penalty for retaining both address and target instruction at the BTB$?$