Part $2\mathrm{.}2[15$ points$]$ A SRAM has an $8-$bit data bus and a $5-$bit address bus. The SRAM function table is shown below:

$\backslash$table$[[$WE$,$CS$,$OE$,$I$/$O$,$Function$],[$X$,$L$,$X$,$High$-$Z$,$Standby$],[$L$,$H$,$L$,$High$-$Z$,$Output Disabled$],[$L$,$H$,$H$,$Dour,Read Data$],[$H$,$H$,$X$,$DII,Write Data$]]$

The CS$,$ WE$,$ and OE signals in the above function table are high active. Design the above SRAM in VHDL

library ieee;

use ieee.std$\_$logic$\_1164.$all;

use ieee.std$\_$logic$\_$unsigned.all;

entity ram is

port $($ address :

data :$-$

wes : $,$ on ram;

architecture beh$\_$ram of ram is

end beh$\_$ram;